Indian-origin scientist leads Stanford team to build a 'high-rise' chip

Stanford scientists have developed 'high rise' chips that "could leapfrog the performance of the single-story logic and memory chips," in use today.

Those circuit cards are like busy cities in which logic chips compute and memory chips store data. But when the computer gets busy, the wires connecting logic and memory can get jammed.

The Stanford approach would end these jams by building layers of logic atop layers of memory to create a tightly interconnected high-rise chip.

Many thousands of nanoscale electronic "elevators" would move data between the layers much faster, using less electricity, than the bottleneck-prone wires connecting single-story logic and memory chips today.

Subhasish Mitra, professor of electrical engineering and computer science, and HS Philip Wong from Stanford's school of engineering are set to describe the new high-rise chip architecture in a paper at the "IEEE International Electron Devices Meeting" in San Francisco this week.

"This research is at an early stage but our design and fabrication techniques are scalable," Mitra said.

"With further development this architecture could lead to computing performance that is much, much greater than anything available today," he added.

The researchers' innovation leverages three breakthroughs.

The first is a new technology for creating transistors, those tiny gates that switch electricity on and off to create digital zeroes and ones.

The second is a new type of computer memory that lends itself to multi-story fabrication.

The third is a technique to build these new logic and memory technologies into high-rise structures in a radically different way than previous efforts to stack chips.

Source : Phys.org